ISEC Test of Time Award

ISEC 2011 Paper

Mahesh Shirole, VJTI Mumbai, India

Title of the Talk — Generation of Improved Test Cases from UML State Diagram using Genetic Algorithm

Authors — Mahesh Shirole, Amit Suthar, Rajeev Kumar

Abstract — An UML statechart diagram is used to model the dynamic aspects of object oriented software systems. A Finite State Machine (FSM) and an Extended Finite State Machine (EFSM) are commonly used for Model Based-Testing (MBT). A test case generation from FSM is easy due to unconditional transition from state to state by traversal. A test case generation from EFSM needs to satisfy the guard condition before transition from state to state. Testing from EFSM is difficult due to unfeasible paths and test data. This paper proposes a search-based approach to find feasible transition sequences and test data generation. The Unified Modeling Language specifications are translated into extended flow graphs. An Extended flow graph from EFSM specifies the control and data flow in a statechart diagram. To guide the feasible transition path a genetic algorithm (GA) framework is proposed. It is shown that the test cases so generated yield an improved test set.

Short Bio of Presenter

Mahesh Shirole

Head CE & IT Department, Associate Professor, VJTI- Mumbai, India.

Mahesh Shirole's teaching and research activities span over 20 years in the areas of software engineering, blockchain technology, networking, etc. Currently, he is Head and Associate Professor of Computer Engineering at Veermata Jijabai Technological Institute (VJTI), Matunga, Mumbai-400 019. He holds a doctoral degree in Computer Engineering from Indian Institute of Technology, Kharagpur (IITKGP), a master’s degree in Computer Engineering from VJTI, Mumbai, and a bachelor’s degree in Computer science and engineering from Walcahand College of Engineering, Sangali. Mahesh is a powerful force in the workplace and uses his positive attitude and tireless energy to encourage others to work hard and succeed.